This invention relates to transistor-transistor logic (TTL) circuits and more particularly to the prevention of transistor saturation in TTL circuits while maintaining standard TTL input and output voltage levels over a wide range of temperature.
TTL circuits are widely used because of their logic flexibility, low power dissipation and fast switching capability. These circuits, however, encounter problems when operated over a wide range of temperatures because of the dependence of P-N junction characteristics on temperature variations
In order to achieve the fast turn on transition desired in TTL circuits, high drive currents are generally used for driving the circuit's output transistor. These high currents, however, also drive the transistor into deep saturation which results in excess charge build-up in the driven transistor. This excess charge build-up results in a longer turn-off delay because of the time it takes for the built up charge to dissipate. It is this long turn-off delay which has prevented the use of TTL circuits in many high speed applications, particularly in high temperature environments where saturation is attained as a result of an increase in minority carriers. On the other hand, when a TTL circuit is operated at low temperatures, saturation of the output transistor is not a concern due to the reduction of minority carriers which are present at low temperatures. Instead, maintaining the low level output voltage (V.sub.OL) within the standard TTL level of approximately 0.4 v becomes a problem. As the temperature decreases, the offset voltage of the transistor increases. At very low temperatures, this can be significant enough to cause the V.sub.OL to increase above the standard level of 0.4 v. Thus, if a TTL circuit is to operate at fast switching speeds and within TTL output specifications, a means must be included in the circuit which will prevent the output transistor from saturating at high temperatures while providing a reference voltage for the output such that V.sub.OL falls within TTL specifications at low temperatures.
Several methods have been implemented for preventing saturation of the output transistor even at high temperatures, although the prior art does not address the problem of also keeping within the V.sub.OL specifications at low temperatures. A common antisaturation technique uses a Schottky diode in shunt with the base collector junction of a common emitter NPN output transistor. Because the Schottky diode has a lower forward voltage (V.sub.F) than the forward biased voltage of the shunted junction (V.sub.BC), the Schottky diode clamps the junction voltage to a level lower than the collector-base forward biased voltage, thereby preventing saturation of the output transistor. The problem with using Schottky diodes is that both the forward voltage of the Schottky diode and the forward biased voltage of the P-N junctions of the output transistor vary as a function of temperature, approximately -1 mV/.degree.C. and -2 mV/.degree.C. respectively. As the temperature increases, the relative difference betweeen V.sub.F and V.sub.BC decreases. This results in the Schottky clamp losing its effectiveness at preventing saturation of the output transistor at high temperatures.
Even in this arrangement, during low temperature operation the V.sub.OL still remains a potential problem. Although the difference between the levels of V.sub.F and V.sub.BC increases as temperature drops, thereby assuring effective clamping against saturation, a drop in temperature produces an increased offset voltage of the clamped transistor which can cause V.sub.OL to exceed the standard TTL output voltage level. Thus, the use of Schottky diodes is not effective as an antisaturation device when the circuit is to be operated at high and low temperatures.
A different approach in preventing saturation which does not rely on the use of Schottky devices is taught in Wiedmann, U.S. Pat. No. 3,676,713, whereby by an NPN transistor is used instead of a Schottky diode to shunt the collector-base voltage of the output transistor. The clamping technique of Wiedmann does not allow for the use of standard TTL input voltage levels in the circuit. Instead of utilizing the 0.8 v to 2.0 v, input threshold levels of TTL, the Wiedmann circuit requires an input of less than 0.8 v. Thus, Wiedmann's circuit can not be utilized in standard TTL circuitry.
Additionally, Wiedmann uses a collector-base junction voltage as a reference voltage for the antisaturation circuit. Typically in NPN transistors, the collector is doped less than the emitter thereby producing a larger parasitic resistance in series with the collector-base junction as opposed to the base-emitter junction. By using the collector-base junction as a reference voltage, the range with which the reference voltage will linearly correspond with the collector current will be small. As the collector current increass through the junction, the parasitic resistance of the junction becomes more prominent. Thus, at high collector currents a small change in the current results in a relatively large change in the reference voltage for the antisaturation circuit.